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Synopsys Leads Effort Towards Open Verification Language

 

April 19, 1999 -- Synopsys Inc., the technology leader for complex integrated circuit (IC) design, today announced its latest industry initiative to solve the verification bottleneck for system on a chip. The company is spearheading a customer-based steering committee to help move the industry towards an open, high-level verification language, based on Synopsys' proven VERA(TM) Hardware Verification Language (VERA HVL). Joining Synopsys in this effort are a number of electronics companies, including AMD, ARM, Cisco, Compaq, Hewlett Packard, LevelOne, Sun and Tensilica. Representatives of these companies will serve on the VERA Steering Committee. By actively leading this effort, Synopsys and VERA users are working to improve the productivity and interoperability of verification design environments.

In addition, Synopsys announced that the application interface to VERA--VERA API -- is available through the Synopsys technology access program, TAP-in(TM), free of charge. With VERA API, third party vendors offering products such as simulators, emulators and code coverage tools can freely integrate them with VERA. This gives VERA users a wider choice of tools and services to incorporate into their environment.


Verification Languages

Designers have been turning towards optimized verification languages because, as designs get more complex, traditional hardware description languages do not contain the high level of abstraction and features necessary for successful functional verification of complex ICs and systems. Yet, these closed languages limit the users' ability to interoperate freely within their design environment, restrict their choices in EDA tools and can require them to learn multiple languages. By sponsoring the VERA Steering Committee, Synopsys is actively working with customers to solve this problem by moving its popular VERA HVL towards an open format which will enable customers and EDA tool vendors to base their verification environments on a single language, optimized for efficient verification.

"Testbench automation using languages like VERA HVL is one of the few areas in today's design flow where users can achieve a three to ten times productivity improvement," said Dave Burow, senior vice president and general manager of the High Level Verification Group at Synopsys. "With VERA's proven success at many leading companies, opening VERA is the next step to expand its adoption."

The VERA Steering Committee will meet quarterly and will explore additional enhancements for VERA HVL to ensure that it meets the needs of a broad user base prior to making it widely available through the Synopsys technology access program, TAP-in. The first steering committee meeting was held at the International HDL Conference in Santa Clara, CA on April 7, 1999.

"We're excited about the prospect of an open verification language," said Greg Allen, program manager for system integration and IP/Re-use at Hewlett Packard. "We selected VERA HVL because we found it to be a powerful verification language, yet it is easy to use and support in our environment. By making the VERA HVL a standard, it will level the playing field among other verification tools. This will keep them competitive which in the end, is a big win for us."


VERA HVL

VERA HVL is an intuitive high-level, object-oriented programming language developed specifically to meet the unique requirements of functional verification. VERA HVL enables the user to describe the target application environment, including complex protocols and data objects, at a high level of abstraction, dramatically increasing productivity, readability and re-usability. Designers who use VERA HVL report up to a 10x reduction in the amount of testbench code they need to develop, saving significant time in getting new chips to market. In addition, VERA testbenches are HDL and simulator neutral--the same testbench can drive Verilog or VHDL designs and cycle- or event-based simulators. Furthermore, with VERA CORE the testbench can be securely distributed for verifying IP based systems on a chip.

"We have been using VERA for several years, and are very pleased with the product," said Nozar Azarakhsh, design/verification manager at Cisco Systems' Cable Solutions Engineering Team. "We view Synopsys' thrust towards standardizing VERA HVL as a positive move, which will promote and accelerate the open development of VERA HVL-based products and services, and will secure our tools, training, and code base investment."


High Level Verification

Synopsys offers a powerful suite of functional verification products and consulting services. In addition to testbench automation, the Synopsys verification solution includes VCS(TM), the industry's fastest Verilog simulator, Cyclone(R)/VSS(TM) for high-performance VHDL simulation, a comprehensive range of Logic Modeling(R) simulation models, the innovative Eaglei(R) hardware/software co-verification tools and, CoverMeter(TM) code coverage analysis to help meet the challenges of functional verification of complex designs. Synopsys complements this suite with a complete static verification offering, which includes formal verification, static timing analysis and automatic test pattern generation. These tools conform to industry standard practices to ensure easy integration with customer design environments.

For more information about VERA HVL or other Synopsys verification products, contact your local Synopsys representative, call 1-800-346-6335 or email verify@synopsys.com.


 

Synopsys Editorial Contact
The Hoffman Agency
Phone: 408-286-2611
10 S. Third St., 5th Floor
San Jose, CA 95113

 

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