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World's Top Foundries Choose Mentor Graphics' "DFM
Silicon Partners" Program

 

Customers Get Improved Chip Yield, Performance and Time-to-Market

WILSONVILLE, Ore. - November 16, 1998 - Mentor Graphics Corporation (NASDAQ: MENT), the leader in physical verification and extraction for deep submicron integrated circuits (ICs), today announced that the world's top four deep submicron foundries have joined its newly formed Design for Manufacture (DFM) Silicon Partners program. They include: Chartered Semiconductor Manufacturing, IBM's Microelectronics Division, TSMC and UMC Group.

By providing foundry-specific information derived from the manufacture and measurement of a test chip, Mentor Graphics and its foundry partners offer joint customers the ability to verify and "tune" designs to a specific process technology. Design customers get increased chip yield and performance, and cut time-to-market. Test chips are already in progress at both 0.35 and 0.25 micron at multiple foundries.

"Mentor Graphics is committed to partnering with foundries to help IC customers achieve dependable first-pass success for complex deep submicron designs," said Leigh Anderson, foundry relations manager, Mentor Graphics Corporation. "To have all the significant players in the deep submicron arena sign on as charter members of the DFM Silicon Partners program confirms the strong demand for manufacturing calibration using industry-standard verification and analysis tools. We're excited about the results we've obtained with our foundry partners and their customers. We've already received test chips back from a leading 0.25-micron process, and have schedules set for 0.18 micron. Calibre design rule checking (DRC) rule decks at 0.18 micron are already in use at joint customers."

Through DFM Silicon Partners, foundries and Mentor Graphics collaborate to deliver silicon-calibrated technology files and models to support mutual customers who use Mentor Graphics' deep submicron verification and interconnect solutions, including the Calibre tool suite, the xCalibre tool suite and future verification tools. Using these qualified DRC rule decks and parasitic extraction models, design customers without fabrication facilities can more effectively validate deep submicron designs prior to manufacture, avoiding risk and achieving silicon goals. Design houses can focus on chip design and quicker time-to-market, while avoiding the cost of duplicated test chip efforts.

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of $468 million and employs approximately 2,500 people worldwide. Company headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

 

Mentor Contact
Michelle Clancy
Corporate Communications
Mentor Graphics Corporation
503/ 685-4830
michelle_clancy@mentor.com

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